Imaging sensor arrays are used in a large variety of different applications. In some applications, a large array area size is desirable, for example medical X-ray imaging, telescope focal planes and X-ray detectors in a synchrotron. In practice, such a large detection area may be achieved by tiling several smaller detector units. To avoid the loss of parts of the image, the gaps between each individual unit should be as small as possible.
Often, CMOS image sensors or semiconductor detectors bump-bonded to a CMOS readout chip are used. A CMOS imaging sensors (CIS) is a pixelated electronic device which can sense electromagnetic radiation (often light) and translate this into a readable output voltage. In a standard CIS, each pixel converts received radiation to voltage and stores it until a read-out phase. FIG. 1 shows a known type of CIS 10. This comprises: a plurality of pixels 20; row addressing circuitry 30; row addressing signal lines 35; read-out circuitry 40; and read-out lines 45. During read-out, a row is addressed using the row circuitry 30 which is located along one edge of the device. All pixels in that row are read out along a respective column read-out line 45. Each pixel in a different column is coupled to the same read-out line 45. In order to produce a uniform image, all of the pixels are desirably identical.
In the CMOS part of the detector, control and read-out electronics is therefore typically provided on at least two sides of the sensor array. Read-out amplifiers and column controlled circuitry are often provided on the bottom of the array and row addressing circuits are often provided on the left-hand side, as shown in FIG. 1. In view of the circuitry present on these two sides, any attempt to tile sensor arrays using these sides will result in significant gaps in the resultant composite array. If the sensor arrays are square and only a 2×2 tiling is necessary, these gaps do not cause a problem.
Nevertheless, larger imaging sensors are increasingly desirable. This is difficult to achieve in view of the limitations discussed above. A known approach to increase the number of buttable sides (that is, sides of the pixel array along which no circuitry is placed and which can therefore abut other sensor arrays to create a composite device) is to place the addressing circuitry and read-out circuitry along the same edge of the pixel array. For example, U.S. Pat. No. 7,009,646 considers such an approach.
To create even larger composite sensors, the individual sensor arrays making up the composite should preferably be as large as possible themselves. The largest possible sensors are the size of a full CMOS wafer and are called wafer-scale. Such large-scale individual devices are produced using a process known as stitching. Identical blocks of circuitry are repeated across the sensor. Selecting a single row of pixel sensors when all of the circuitry blocks are the same creates significant difficulties.
When stitching is combined with the strategy of placing all electronic circuitry on only one edge of the sensor array, there is a further challenge. Devices where row addressing can be carried out essentially using horizontal lines and read-out essentially using vertical lines have a symmetrical nature. When all of the electronic circuitry is placed along a single edge, both addressing and read-out rely on lines with the basically same orientation. A repeatable arrangement of pixel sensors and addressing lines from which a single row can be selected is not easy. Moreover, it is desirable that the sensor array be produced using as few different types of repetition unit (known as stitching blocks) as possible. This not only results in a device that is easier and less costly to manufacture, but also improves the likelihood that each pixel sensor will be the same. Image quality is improved thereby. Achieving all of these aims remains a difficulty.